1 octal transparent d-type latches w ith 3-state outputs general description 74HC373 is fabricated with high-speed silicon gate cmos technology. it has the high noise immunity and low power consumption of standard cmos integrated circuits. the eight latches in 74HC373 devices are transparent d-type latches. while the latch-enable (le) input is high, the q outputs follow the data (d) inputs. when le is low, the q outputs are latched at the levels that were set up at the d inputs. an output-enable input (oe) makes the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high- impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. oe does not affect the internal operations of the latches. old data can be retained or new data can be entered while the outputs are off. these 8-bit latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. they are particularly suitable for implementing buffer registers, i/o ports, bi-directional bus drivers, and working registers. features ? wide operating supply voltage range: 2-6v ? 8 high-current latches with 3-state outputs in a single package ? full parallel access for loading ? low input current: 1 a (max.) ? low power consumption: 80 a (max.) logic diagram oe (1) le (11) functional description truth table inputs outputs oe le d q l h h h l h l l l l x q 0 h x x z h = high level (steady state). l= low level (steady state) x = irrelevant (any input, including transitions) 1d c1 2 d c1 3 d c1 4 d c1 5 d c1 6 d c1 7 d c1 8d c1 1d (3) 2d (4) 3d (7) 4d (8) 5d (13) 6d (14) 7d (17) 8d (18) 1q (2) 2q (5) 3q (6) 4q (9) 5q (12) 6q (15) 7q (16) 8q (19)
2 absolute maximum ratings parameter value unit dc supply voltage (vcc) - 0.5 ~ + 7.0 v dc input or output voltage (v in , v out ) -0.5 to vcc +0.5 v dc current drain per pin, any output (i out ) 35 ma dc current per pin, vcc or gnd (icc) 70 ma storage temperature( t stg ) -65 ~ +150 note : 2. all unused inputs of the device must be held at vcc or gnd to ensure proper device operation. dc electrical characteristics ( apply across temperature range unless otherwise specified) t a -40 ~ +85 parameter test conditions vcc min. typ. max. min. max. unit 2v 1.9 1.998 1.9 4.5v 4.4 4.499 4.4 i oh = -20ua 6v 5.9 5.999 5.9 i oh = -6ma 4.5v 3.98 4.3 3. 84 v oh v i =v ih or v il i oh =-7.8ma 6v 5.48 5.8 5. 34 v 2v 0.002 0.1 0.1 4.5v 0.001 0.1 0.1 i ol = 20ua 6v 0.001 0.1 0.1 i ol = 6ma 4.5v 0.17 0.26 0.33 v ol v i =v ih or v il i ol = 7.8ma 6v 0.15 0.26 0.33 v i i v i = v cc or 0 6v
3 timing requirements over recommended operating temp erature ( unless otherwise specified ) t a = 25 -40 ~ +85 parameter v dd min max min max unit 2.0 v 80 100 tw pulse duration, le high 4.5v 16 20 ns 6.0 v 14 17 2.0 v 50 63 tsu setup time, data before le 4.5v 10 13 ns 6.0 v 9 11 2.0 v 20 24 th hold time, data after le 4.5v 10 12 ns 6.0 v 10 12 ac electrical characteristics over recommended oper ating temperature, cl = 50 pf ( unless otherwise specified ) parameter from to v dd t a = 25 -40 ~ +85 (input) (output) min typ max min max unit 2.0 v 58 150 190 d q 4.5v 15 30 38 ns 6.0 v 13 26 32 2.0 v 73 175 220 4.5v 18 35 44 tpd le any q 6.0 v 15 30 38 ___ 2.0 v 65 150 190 ten oe any q 4.5v 17 30 38 ns 6.0 v 14 26 32 2.0 v 50 150 190 4.5v 15 30 38 tdis ___ oe any q 6.0 v 13 26 32 2.0 v 28 60 75 t t any q 4.5v 8 12 15 ns 6.0 v 6 10 13
4 ac electrical characteristics over recommended oper ating temperature, cl = 150 pf ( unless otherwise specified ) parameter from to v dd t a = 25 -40 ~ +85 (input) (output) min typ max min max unit 2.0 v 82 200 250 d q 4.5v 22 40 50 ns 6.0 v 19 34 43 2.0 v 100 225 285 4.5v 24 45 57 tpd le any q 6.0 v 20 38 48 ___ 2.0 v 90 200 250 ten oe any q 4.5v 23 40 50 ns 6.0 v 19 34 43 2.0 v 45 210 265 t t any q 4.5v 17 42 53 ns 6.0 v 13 36 45 ac switching waveform and ac test circuit voltage waveforms pulse durations voltage waveforms setup & hold and input rise & fall times voltage waveforms propagation delay and output transition times voltage waveforms enable and disable times for 3-state outputs t w 50% 50% 50% 50% low-level pulse v cc 0v v cc 0v high-level pulse tr 50% 10% 90% 90% 50% 10% t f vcc 0 v input 0 v input 50% t su vcc t h reference data 50% 50% 50% 90% 50% 10% tpzl tplz tphz vcc 0 v v ol v oh , 0 v tpzh , vcc output control (low-level enabling) output waveform1 output waveform 2 , vcc tplh tr tphl t f t f tr tphl tplh 50% 50% 50% 10% 90% 90% 50% 10% 90% 50% 10% 90% 50% 10% input in-phase output out-of-phase output vcc 0 v v oh v ol v oh v ol
5 parameter r l c l s1 s2 t pzh open closed t en t pzl 1k ? 50 pf or 150 pf closed open t phz open closed t dis t plz 1k ? 50 pf closed open t pd or t t - 50 pf or 150 pf open open notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal condit ions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal condition s such that the output is high except when disabled by the output control. c. phase relationships between waveforms were chose n arbitrarily. all input pulses are supplied by generators having the following characteristics: prr 0 1 mhz, zo = 50 ? , t r =6ns, t f =6ns. d. the outputs are measured one at a time with one input transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t plh and t phl are the same as t pd . pin description pin no. symbol description 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 10 1 11 20 1d - 8d 1q - 8q gnd oe le vcc data inputs outputs ground (0v) output-enable latch-enable positive power supply 1d 2d 2q 3q 7d oe 1q 6d 1 10 20 11 4d 5d 3d 4q gnd 5q le 8d 8q 7q 6q vcc pin configuration (dip-20) logic symbol 1d 2d 3d 4d 5d 6d 7d 8d 1q 2q 3q 4q 5q 6q 7q 8q oe le 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 1 v dd s1 s2 r l test point from output under test c l (see note a)
6 pad diagram the coordinate of each pad 8q (-326.1, -808.7) 4q (237.7, 718.5) v cc (-151.7, -816.1) gnd (42.5, 729.9) oe (82.5, -808.7) le (-160.5, 718.6) 1q (237.7, -808.7) 5q (-326.1, 718.6) 1d (388.3, -673.1) 5d (-476.5, 568.7) 2d (388.3, -457.3) 6d (-476.5, 352.9) 2q (388.0, -132.2) 6q (-476.5, 24.7) 3q (388.0, 25.6) 7q (-476.5, -135.0) 3d (388.1, 351.8) 7d (-476.5, -457.2) 4d (388.1, 567.6) 8d (-476.5, -673.0) note: substrate should be connected to vcc or left it open. 74HC373 pad size = 90 um x 90 um die size = 49 mil x 77 mil 1d 2d 2q 4q 3q 3d 4d 5q le gnd 5d 6d 6q 8d vcc oe 1q 8q 7d 7q
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